Compressed image decompressing device

ABSTRACT

An image processing device which processes a portion of the decompression process including a lot of comparatively complex operations like an inverse discrete cosine transform by software with using a high-performance, general-purpose processor capable of parallel processing, and the other portion of the decompression process which is compara- tively simple but requires frequent access to a memory, e.g., when other frame data is to be read out for processing of encoded interframe predictive image data, or is compara- tively simple but substantially hard to process in parallel, e.g., when variable length coded pixel values are to be decoded, by hardware with the use of a specialized periph- eral circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image processing device fordecompressing compressed image data. In the device, a general-purposemicroprocessor and a specialized circuit cooperate to efficientlydecompress the compressed image data, more specifically, thegeneral-purpose microprocessor executes a portion of the datadecompression process including a lot of arithmetical and logicaloperations by software, whereas the specialized circuit carries out aportion of the decompression process including a lot of operations toread out data from a memory.

2. Description of the Related Art

Since image data is considerably large in volume, the data is usuallyencoded to digital data and further compressed when stored ortransmitted. Many studies have been already made especially in relationto encoding and compressing of moving picture data, which results in astandard format of image data for the MPEG (Moving Picture ExpertsGroup) or the like set by the International Organization for Stan-dardization.

Decompression of image data is necessary so as to reproduce an originalimage data from the compressed image data as represented by movingpicture data meeting the MPEG standard. For this purpose, various LSIsfor decompression of moving picture data, e.g., HDM8211M (HyundaiElectronics America), M65771FP and M65770FP (Mitsubishi Denki KabushikiKaisha), etc. have been devel- oped. The HDM8211M, for example, isdescribed in “Single Chip Performs Both Audio and Video Decoding” (DaveBursky: pp. 77-80; Electronic Design, Apr. 3, 1995).

Those conventional LSIs require an integrated structure of a lot ofoperation units, which increases a hardware scale and costs. Further,those LSIs are constructed for a specific purpose and unusable for otheruses, therefore, making it necessary to develop LSIs of kindsproportional to the kinds of image data. Thus, the conventional LSIslack flexibility.

To solve the above-mentioned problem, decompression of image data bysoftware without employing specialized hard- ware has been tried,whereby some instructions exclusive for processing the MPEG image dataare added to a general-purpose microprocessor. The idea is described in“Acceler- ating Multimedia with Enhanced Microprocessors” (Ruby B. Lee:pp. 22-32; IEEE Micro, April 1995). The decom- pression process for theMPEG standard image data by software applies an excessive load on theconventional image processing device in spite of a limited operationalefficiency or a limited memory access speed of the general-purposeprocessor. Therefore, the conventional decompres- sion process bysoftware actually achieves low-quality mov- ing picture data ordecompresses image data in non-real time, and it is insufficient fordecompressing moving picture data in real time with high quality.

SUMMARY OF THE INVENTION

The present invention was devised to overcome the afore- mentionedproblems. A main object of the invention is to provide an imageprocessing device in which a general-purpose microprocessor forprocessing an image data by software and a peripheral circuit forprocessing the image data by hardware cooperatively work thereby toefficiently decompress the image data such as represented by theMPEG-standard image data, and to relatively lower produc- tion costs.

The image processing device of the invention executes a portion of thedecompression process which includes a lot of complex operations like aninverse discrete cosine transform by software with the use of ahigh-performance, general-purpose processor capable of parallelprocessing. In the meantime, the device of the invention executes theother portion of the decompression process which is relatively simple,but requires frequent memory access, for example, when other frame dataare to be read out to process encoded interframe predictive image data,or is relatively simple but substantially hard to process in parallel,e.g., in case of decoding of variable length coded pixel values, byhardware with the use of a specialized peripheral circuit. Accordingly,the general-purpose processor that processes image data by software andthe peripheral circuit that processes image data by hardware workcooperatively.

In the image processing device of the invention, a spe- cializedperipheral circuit such as a VLC (variable length code) decoder and/or ablock loader executes a process among necessary processes by hardwarewhich requires a lot of data to be read out from a large-capacity memorybut relatively simple, while a microprocessor processes a pro- cess bysoftware which includes a lot of complicated opera- tions such as aninverse discrete cosine transform.

In the image processing device of the invention, a spe- cializedhardware and a microprocessor cooperatively pro- cess image data likethrough a pipeline thereby to restrict the total scale of hardware, andto enhance a processing speed even when a large-capacity memory of arelatively low processing speed is used. Hence, the device isinexpensive with a good performance.

Further, in the image processing device of the invention, amicroprocessor covers complicated operations by soft- ware. The deviceis applicable not only to the MPEG standard but to other imageprocessing methods. Accordingly, the device can flexibly cope with everymethod through modification of software.

The above and further objects and features of the inven- tion will morefully be apparent from the following detailed description withaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an example of the configuration of asystem including a first embodiment of an image processing device of theinvention connected to a memory;

FIG. 2 is a diagram showing an instruction format of a microprocessor inthe image processing device of the inven- tion;

FIG. 3 is a diagram showing detailed contents of a format field of aninstruction of the microprocessor in the image processing device of theinvention;

FIG. 4 is a diagram showing detailed contents of an execution conditionfield of the instruction of the micropro- cessor in the image processingdevice of the invention;

FIG. 5 is a diagram showing an example of the structure of bits ofsub-instructions of the microprocessor in the image processing device ofthe invention;

FIG. 6 is a diagram showing an example of the structure of registers ofthe microprocessor in the image processing device of the invention;

FIG. 7 is a diagram showing contents of a processor status word of themicroprocessor in the image processing device of the invention;

FIG. 8 is a block diagram showing an example of the total structure ofthe microprocessor in the first embodiment of the image processingdevice of the invention;

FIG. 9 is a block diagram showing an example of the structure of aninteger functional unit of the microprocessor in a first embodiment ofthe image processing device of the invention;

FIG. 10 is a block diagram showing an example of the structure of ablock loader of the microprocessor in the first embodiment of the imageprocessing device of the inven- tion;

FIGS. 11A-11C are schematic diagrams explanatory of a compression(encoding) process for moving picture data;

FIGS. 12A and 12B are schematic diagrams explanatory of a decompression(decoding) process for compressed (encoded) moving picture data;

FIG. 13 is a flowchart showing a procedure by block data which is a partof algorithm used when the microprocessor in the first embodiment of theimage processing device of the invention processes image data accordingto the MPEG standard;

FIG. 14 is a block diagram showing an example of the configuration of asystem including a second embodiment of an image processing device ofthe invention connected to a memory;

FIG. 15 is a block diagram showing an example of the whole structure ofa example of an entire microprocessor in the second embodiment of theimage processing device of the invention;

FIG. 16 is a block diagram showing an example of the configuration of asystem including a third embodiment of an image processing device of theinvention connected to a memory;

FIG. 17 is a block diagram showing an example of the configuration of asystem including a fourth embodiment of an image processing device ofthe invention connected to a memory;

FIG. 18 is a block diagram showing an example of the configuration of asystem including a fifth embodiment of an image processing device of theinvention connected to a memory;

FIG. 19 is a block diagram showing an example of the configuration of asystem including a sixth embodiment of an image processing device of theinvention connected to a memory;

FIG. 20 is a block diagram showing an example of the configuration of asystem including a seventh embodiment of an image processing device ofthe invention connected to a memory;

FIG. 21 is a block diagram showing an example of the configuration of asystem including an eighth embodiment of an image processing device ofthe invention connected to a memory; and

FIG. 22 is a block diagram showing an example of the configuration of asystem including a ninth embodiment of an image processing device of theinvention connected to a memory.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[Embodiment 1]

(1) Entire architecture

FIG. 1 is a block diagram showing an example of the construction of afirst embodiment of an image processing device of the invention in asystem, to which a memory is connected. In the figure, numeral 1 denotesa chip on which is mounted the image processing device of the invention,which is connected via a data bus 3 and an address bus 4, etc. to anexternal memory 2 composed of plural DRAM chips.

The image processing device of the invention mainly processes threekinds of data, that is, video data meeting the MPEG standard wherebycompressed image data of 30 frames is decompressed per second, eachframe being com- posed of 90×60=5400 blocks and each block being com-posed of 8×8=64 pixels, audio data attached to the video data, andsystem data relating to the operation of a decoding system.

An operational unit which plays a central role in the image processingdevice of the invention includes a first microprocessor 10 and a secondmicroprocessor 11. The first and second microprocessors 10, 11distribute the load according to a multiprocessing method thereby toprocess image data with high efficiency.

In the figure, numeral 12 and 13 respectively denote first and secondhigh-speed memories. The first and second high-speed memories 12, 13which function as local memo- ries for the microprocessors 10, 11 areconnected to the first and second microprocessors 10, 11 via buses 24,25, respec- tively.

A VLC (variable length code) decoder 14 decodes a variable-length-codedimage data of the above-mentioned blocks each composed of 64 pixels intodata of fixed length 64 pixels, and outputs the decoded data to thehigh-speed memories 12, 13 through an internal bus 20.

A block loader 15 reads out the block data of an adjacent frame which isto be added with differential data according to the interframepredictive coding method from the external memory 2 and outputs theread-out data to the high-speed memories 12, 13 through the internal bus20. The VLC decoder 14 and block loader 15 connected to the high-speedmemories 12, 13 via the internal bus 20 arbitrate a bus access right inorder to write data in the high-speed memories 12, 13. The internal bus20 consists of an address bus (IA bus) and a data bus (ID bus).

An instruction cache 16 is used by the first and second microprocessors10, 11 in common. The instruction cache 16 caches instructions fetchedfrom the external memory 2 via an external bus 21 and supplies the firstand second microprocessors 10, 11 with the instructions. The instructioncache 16 can supply the first and second microprocessors 10, 11 with thesame instructions, simultaneously, or can supply only either one of thetwo with the instructions. The external bus 21 connecting the imageprocessing device of the invention and the external memory 2 includes anaddress bus (EA bus) and a data bus (ED bus).

An image data output circuit 17 reads out the completely decompressedimage data from the external memory 2 through the external bus 21, thenoutputs the data outside through a bus 28. A serial input circuit 18converts the serial compressed data input through a serial signal line27 from outside into parallel data, then writes the data to the externalmemory 2 via the external bus 21. Therefore, the serial signal line 27is connected to an external antenna or an output line of a digital videodisc (DVD) reproducing apparatus, whereas the bus 28 is connected to animage display device such as a CRT display device.

The first and second microprocessors 10, 11, the VLC decoder 14, theblock loader 15, the instruction cache 16, the image data output circuit17 and the serial input circuit 18 access the external memory 2 byarbitrating the access right to the external bus 21.

A DRAM controller 19, provided between the address bus (EA bus) of theexternal bus 21 and the external memory 2 translates an address outputto the external bus 21 into a row address and a column address foraccessing the external memory 2.

(2) Microprocessor

The first and second microprocessors 10, 11 have the same construction.In this first embodiment, the image processing program includes a periodwhile only the first microprocessor 10 operates, a period while only thesecond microprocessor 11 operates, and a period while bothmicroprocessors 10, 11 operate. But instructions, the constitution ofregisters, and hardware functions of the two microprocessors areessentially the same, and therefore only the first microprocessor 10will be explained here, which applies also to the second microprocessor11.

(2.1) Instruction set and register composition

Formats of instructions of the microprocessor 10 are shown in FIG. 2,namely, a format 101 of two sub- instructions which instruct twooperations by one instruction, and a format 102 of one sub-instructionwhich indicates one operation by one instruction.

The two-operation format 101 includes a format field composed of twoone-bit fields 103 and 104, two container fields 106, 107, and anexecution condition field 105 of 3 bits attached to each of thecontainer fields 106 and 107. The one-operation instruction format 102includes a format field composed of two one-bit fields 103 and 104, acontainer field composed of two fields 108 and 109, and an executioncondition field 105 of 3 bits attached only to the one field 108 of thecontainer field.

FIG. 3 is a diagram showing detailed contents of the format fields 103,104. When a value FM of the format fields is “00”, the instruction is atwo-operation instruction. It means that a sub-instruction specified inthe container_0 field 106 is to be executed in a clock cycle just afterdecoding, and a sub-instruction specified in the container_1 field 107is to be delayed one clock cycle from the execution of thesub-instruction in the container_0.

When a value FM of the format fields 103, 104 is “01”, the instructionis a two-operation instruction. It means that a sub-instructionspecified in the container_0 field 106 and a sub-instruction specifiedin the container_1 field 107 are executed in parallel in a clock cyclejust after decoding.

When a value FM of the format fields 103, 104 is “10”, the instructionis a two-operation instruction. It means that a sub-instructionspecified in the container_1 field 107 is to be executed in a clockcycle just after decoding, and a sub- instruction specified in thecontainer_0 field 106 is to be executed one clock cycle after theexecution of the sub- instruction in the container_1.

When a value FM of the format fields 103, 104 is “11”, the instructionis a one-operation instruction. It means that one sub-instructionspecified in the field composed of the fields 108 and 109 is to beexecuted in a clock cycle just after decoding.

FIG. 4 is a diagram showing detailed contents of the execution conditionfield 105. The execution condition field 105 determines whether thesub-instructions specified in the container fields 106 and 107respectively, and a sub-instruction specified in the container fieldcomposed of the fields 108 and 109 are valid or invalid depending onvalues of status flags F0, F1 of the microprocessor 10 which will beexplained later. That the sub-instruction is valid means here that theoperation result is reflected onto registers, memories or flags, wherebythe operation result defined by the sub-instruction remains. On thecontrary, when the operation is invalid, it means that the operationresult is not reflected on registers, memories, or flags, whereby thesame result as that by a no operation instruction (NOP) remains in theregisters or flags irrespective of the kind of the set operation.

When a value CC of the execution condition field 105 is “000”, theoperation is always valid irrespective of values of the flags F0, F1.When a value CC of the execution condition field 105 is “001”, theoperation is valid solely if the flag F0 is “10” irrespective of a valueof the flag F1. When a value CC of the execution condition field 105 is“010”, the operation is valid if both flags F0 and F1 are “10” when avalue CC of the execution condition field 105 is “011”, the operation isvalid only when the flag F0 indicates “10” and the flag F1 is “11”. Whena value CC of the execution condition field 105 is “101”, the operationis valid only when the flag F0 is “11” irrespective of a value of theflag F1. When a value CC of the execution condition field 105 is “110”,the operation is valid if the flag F0 is “11” and at the same time, theflag F1 is “10”. When a value CC of the execution condition field 105 is“111”, the operation is valid only if both flags F0 and F1 are “11”.When a value CC of the execution condition field 105 is “100”, anoperation is undefined, and the value is never used in an instruction.

FIG. 5 is a diagram showing examples of the bit con- struction of shortsub-instructions each expressed by 28 bits, and a long sub-instructionexpressed by 58 bits. The short operation field has three types offormat 111, 112, 113. The long operation field has one type of format114.

The format 111 is composed of fields 115, 117 for specifying contents ofan operation, a field 121 for specify- ing a register number or animmediate value of 6 bits, and two fields 122, 123 for specifyingregister numbers. In a sub-instruction by the format 111 are included anarithmetic operation, a logic operation, a shift operation, and a bitoperation between registers and between a register and an immediatevalue, or a memory access operation, a jump operation or the like forindirect addressing of a register.

The format 112 is for a sub-instruction with 16-bit data in registers.The format 112 is composed of a field 116 for specifying contents of anoperation, three fields 122, 123, 124 for specifying register numbers,and modification data 118, 120 to the register numbers. Themicroprocessor 10 has 64 general-purpose registers of 32 bits in length(refer to FIG. 6) as will be explained later. The 16-bit data is storedin the high halfword (=the most significant 16 bits) or in the lowhalfword (=the least significant 16 bits) of each general-purposeregister. Therefore, a register number and modifi- cation data of onebit indicating the storing position being in the high halfword or in thelow halfword become necessary to specify a position of an operand of 16bits on the register. To the modification data of the register number118, 120 are assigned 3 bits in total for the above indicating purpose.The format 112 is frequently used for processing 16-bit image data.

The format 113 is a format for a branch sub-instruction. The format 113is composed of fields 115, 117 for specifying contents of an operationand a field 125 for a branch displacement. The operation in the format113 includes a branch sub-instruction and a subroutine branchsub-instruction.

The format 114 is for an operation requiring a 32-bit branchdisplacement or a 32-bit immediate value. The format 114 includes afield 115 for specifying contents of an operation, fields 122, 123, 124for specifying three register numbers, and a field 126 for specifyingthe branch displace- ment or immediate value. The format 114 is used fora complicated arithmetic operation, an arithmetic operation employing alarge immediate value, a memory access opera- tion by indirectaddressing of a register with a large displacement, a branch operationwith a large displacement, a jump operation to an absolute address, etc.

FIG. 6 is a diagram showing an example of the construc- tion ofregisters in the microprocessor 10. The micropro- cessor 10 is providedwith 64 general-purpose registers (R0-R63) 160 of 32 bits each, 6control registers 140 of 32 bits, and 2 accumulators 136 of 64 bits. Thecontrol registers 140 include a processor status word (PSW) 134, aprogram counter (PC) 135, and other specialized registers.

In a sub-instruction by the format 112, the high halfword and the lowhalfword of each of the 64 registers 130 are independently accessible.Moreover, the most significant 32 bits or the least significant 32 bitsof the 2 accumulators 136 can be separately accessed from each other.The contents read out from the general-purpose register (RO) 131 isalways “0”, whereby writing is neglected. The general-purpose register(R63) is a stack pointer (SP) which serves as a user's stack pointer(SPU) 132 or an interruption stack pointer (SPI) 133 depending on avalue of an SM field of the PSW 134.

FIG. 7 is a diagram showing detailed contents of the PSW 134. A highhalfword field 142 of the PSW 134 includes the SM field for switchingthe stack pointer, an AT field for controlling whether to translate anaddress, a DB field for controlling driving of a debugging system, andan IMASK field for controlling the acceptance of an external interrup-tion. A low halfword field 143 of the PSW 134 is a flag field. The flagfield 143 has 8 flags. Flags F0 144 and F1 145 control thevalidity/invalidity of an operation. A value of each flag variesdepending on a result of a comparison operation or an arithmeticoperation. Further, a value of each flag sometimes varies when the flagis initialized by a flag initializing operation or when an arbitraryvalue is written in the flag field 143 by an operation writing the flagvalue. A value in the flag field 143 can be read out through a readingoperation.

(2.2) Hardware architecture

FIG. 8 is a block diagram showing an example of the entire constructionof the microprocessor 10 in Embodiment 1.

A bus interface circuit 163 connects the microprocessor 10 to theexternal bus 21, the instruction cache 16, and the high-speed memory 12.The bus interface circuit 163 is connected inside the microprocessor 10with an instruction fetch unit 161 via an IA bus and a BD bus, and isalso connected to an operand access unit 162 via an OA bus and the BDbus.

The instruction fetch unit 161 fetches an instruction from theinstruction cache 16 or from the external memory 2 via the bus interfacecircuit 163, then transfers the instruction to an instruction mapper 150via an II bus of 64 bits. The operand access unit 162 fetches data fromthe high-speed memory 12 or from the external memory 2 through the businterface circuit 163 to a memory access unit 159, or writes datatransferred from the memory access unit 159 to the high-speed memory 12or to the external memory 2 through the bus interface circuit 163.

The instruction mapper 150 divides the 64-bit instruction transferredfrom the instruction fetch unit 161 into operation fields according tothe format fields 103, 104 included in the instruction (refer to FIGS. 1and 3). Then, the instruction mapper 150 transfers the divided data toan instruction decoding unit 170 in the specified order. At that time,the instruction mapper 150 relocates each operation field to acorresponding decoder among four decoders 151, 152, 153, and 154according to the kind of the operation.

The instruction decoding unit 170 is composed of a PCD 151 which is adecoder for decoding codes of a jump operation or a branch operation, anlAD 152 and an lED 153 which are decoders for decoding codes of anoperation such as an arithmetic operation or a shift operation relatingto operands in general-purpose registers, and an MD 154 which is adecoder for decoding codes of a memory access operation. The decodedresults by the decoders 151, 152, 153, and 154 are supplied to a controlcircuit 155. The control circuit 155 including the PSW 134, controls anoperation unit 180 according to both the decoded result by each decoderin the instruction decoding unit 170 and the contents of the PSW 134.

The operation unit 180 is composed of four blocks, that is, a PC unit156, an integer functional unit 160 consisting of two units, and thememory access unit 159, which respec- tively correspond to the fourdecoders 151, 152, 153, and 154 in the instruction decoding unit 170.

The PC unit 156 is provided with the above-mentioned program counter 135(refer to FIG. 6) or an unshown adder. When an instruction withoutincluding a valid jump opera- tion or a valid branch operation isexecuted, the PC unit 156 calculates a PC value of an instruction to beexecuted next by adding “8” to a PC value of the currently executedinstruction. Or, when a jump operation or a branch operation isexecuted, the PC unit 156 calculates a PC value of a jumping destinationby adding a branch displacement to a PC value of the currently executedinstruction or by calcu- lating an address according to an addressingmode specified by the operation.

The integer functional unit 160 is provided with the general-purposeregisters 130 with seven ports each, the control registers 140 and theaccumulators 136 mentioned earlier (refer to FIG. 6), and a barrelshifter, an ALU, and a multiplier which will be explained later (referto FIG. 9). The unit 160 consists of two integer functional mechanisms,i.e., IA unit 157 and IE unit 158 which execute integer operations inparallel. The PC unit 156, and the IA unit 157 and IB unit 158 of theinteger functional unit 160 work independently, but mutually transmit orreceive data via an S bus or a D bus if necessary.

The memory access unit 159 cooperate with the IA unit 157 or the IE unit158 of the integer functional unit 160 to transmit or receive data to orfrom the operand access unit 162.

The operation unit 180 is connected to the instruction fetch unit 161via a JA bus and to the operand access unit 162 via an AA bus and a DDbus thereby to transmit or receive an instruction address, a dataaddress and data to or from the instruction fetch unit 161 and theoperand access unit 162, respectively.

FIG. 9 is a detailed block diagram showing an example of theconstruction of the integer functional unit 160 together with theconnection relationship between the integer func- tional unit 160 andthe memory access unit 159. The integer functional unit 160 is composedof a register file 166 and two operation units 167, 168.

The register file 166 includes the general-purpose regis- ters 130, thecontrol registers 140 shown in FIG. 6 and mentioned earlier, which areshared by the IA unit 157 and the IB unit 158. The operation unit 167 isincluded in the IA unit 157 and the operation unit 168 is in the IB unit158. That is, the IA unit 157 is composed of the operation unit 167 andthe register file 166, while the IB unit 158 is composed of theoperation unit 168 and the register file 166.

The general-purpose registers 130 in the register file 166 and theoperation units 167, 168 are connected via three buses each, whereby twooperations are executable inde- pendently. The general-purpose registers130 are connected to the memory access unit 159 via another bus. Theopera- tion unit 167 is provided with an ALU 167 A, a barrel shifter167B, and a multiplier 167M, whereas the operation unit 168 is providedwith an ALU 168A, a barrel shifter 168B, and a multiplier 168M. It isnot shown in the figure, but one of the accumulators 136 is set in theoperation unit 167 and the other one of the accumulators 136 isinstalled in the operation unit 168. The multiplied results by themultipliers 167M, 168M are thus cumulatively added or subtracted andheld in the accumulators.

(2) Block loader

FIG. 10 is a detailed block diagram showing an example of theconstruction of the block loader 15. In the figure, an input queue 171reads and buffers data of 8 bytes or 9 bytes from the external memory 2every properly arranged 4 bytes, and outputs the data one byte by onebyte. However, a length of data read by the input queue 171 from theexternal memory 2 at one time depends on where a starting address of thedata is located to a boundary of the 4 bytes.

A latch 172 latches data of one byte output from the input queue 171previously to the currently output data.

A register (Offset) 173 is for storing an offset address which isnecessary to read out pixel data of the (n+1)th row following that ofthe n'th row in order to load data of 8×8 pixels block by block from theexternal memory 2.

A register (IAR) 174 is for holding an address when pixel data iswritten to either of the high-speed memories 12 and 13. The register 174has an increment function of address by four. The address held by theregister 174 is output to the IA bus of the internal bus 20. A register(EAR) 175 is for holding an address when pixel data is read from theexternal memory 2. The register 175 having an increment function of anaddress by four. The address held by the register 175 is output to theEA bus of the external bus 21.

An adder 176 adds output data from the input queue 171 to the datalatched by the latch 172, then writes the added result to an outputqueue 177, or adds values of the registers 173, 175 and writes the addedvalue to the register 175. The output queue 177 buffers two chunks of16-bit data output form the adder 176 and outputs the data to thehigh-speed memory 12 or 13 by 4 bytes.

The above-mentioned input queue 171 and registers 173, 174, 175 have aninput route from the ED bus of the external bus 21. The input queue171,. the latch 172, and the registers 173, 175 have an output route tothe adder 176. The input queue 171 also has an output route to the latch172. The adder 176 has further output routes to the register 175 and theoutput queue 177.

In processing the MPEG standard moving picture data, the frame data isprocessed by the full pel or by the half pel as interframe predictivedata. When processing data by the full pel, the adding process of thedata output from the input queue 171 to the data latched by the latch172 at the adder 176 is unnecessary. In this case, the 8-bit data outputfrom the input queue 171 is extended by the adder 176 to data of 16 bitswith zeros and written into the output queue 177.

On the other hand, when the data is processed by the half pel, the 8-bitpixel value output from the input queue 171 is added to the 8-bit pixelvalue output from the latch 172 at the adder 176, and the sum of theadjacent two pixel values of 16 bits is written into the output queue177. Therefore, one pixel of the predictive data is always expressed by16 bits in the block loader 15. In the result, the output queue 177always writes in the high-speed memory 12 or 13 data where one pixel is16 bits and every row of the block is constituted of 8 chunks of datawhether the predictive data is processed by the half pel or full pel.

(4) Processing example of the MPEG standard moving picture data

Before explaining processing of moving picture data by the imageprocessing device of the invention, how to process the MPEG standardmoving picture data (compression of the original picture anddecompression to reproduce the original) will be schematically explainedbelow.

(4.1) Outline of processing of the MPEG standard moving picture data

The image processing device of the invention decom- presses the codeddata obtained by compressing a moving picture image. The coded data isbasically input from outside via the serial signal line 27. For suchcompression of the moving picture data as above, the following threemethods are mainly used. A first method is a compression by means of anintraframe correlation utilizing a correlation of pixels in the sameframe. A second method is a compression by means of an interframecorrelation using a differential value of data of corresponding pixelsof frames. The differential value between the corresponding pixels ofthe frames varies considerably a little as compared with raw data. Athird method is a compression depending on an uneven distribu- tion ofappearance probabilities of codes, wherein a variable length code (VLC)is used. The third method is applied to the differential data (code)obtained by the second method. Concretely, a code of a short bit lengthis assigned to data showing a high appearance probability, whereas acode of a long bit length is assigned for a code of data showing a lowappearance probability, so that data is compressed in vol- ume.

The first method by means of the intraframe correlation will beexplained here. As shown in FIG. 11A, an original picture image of oneframe composed of 720×576 pixels is divided into blocks each comprising8×8=64 pixels, and one of the blocks is shown in FIG. 11A. In thefigure, 64 pixels are denoted by a₁-a₆₄ each of which has a random valueat first. Each block of 8×8=64 pixels shown in FIG. 11A is compressed bymeans of the intraframe correlation. Specifically, the original pictureimage shown in FIG. 11A is transformed by the discrete cosine transform(DCT) in the first place.

When a so-called orthogonal transform is carried out to a square area ofa natural picture image, the natural picture image is graduallytransformed sequentially from an average picture image having a uniformpixel value all over the area to a finer picture image. A finer pictureimage among the thus-obtained picture images of different finesses isnamed as a picture image of a higher frequency. Therefore, the naturalpicture image expressed is a pile of a plurality of images obtainedthrough the transform from a lower fre- quency term (average image) to ahigher frequency term.

According to the MPEG standard, the above-mentioned DCT is adopted asone kind of the orthogonal transform. The image subjected to the DCT hasa characteristic that large pixel values concentrate on lower frequencyterms after the transform although they are scattered at random beforethe transform. Consequently, it is possible to compress data by removingdata of the higher frequency terms from the image data transformed bythe DCT. More specifically, transform- ing of the original picture imageof FIG. 11A by the DCT achieves an image data as shown in FIG. 11B whichhas coefficients b₁-b₆₄ of pixels arranged zigzag from the lowerfrequency term to the higher frequency term.

In the next place, the coefficient of each pixel of the image datatransformed as above is divided by a prescribed divisor D and theremainder is rounded, thereby to quantize the image data. Accordingly,the image data of one frame is compressed. More concretely, quantizingof the image data transformed by the DCT in FIG. 11B results in imagedata as shown in FIG. 11e. In the image data in FIG. 11C, only thequotients c₁-c₅ are obtained in the lower frequency terms and thequotients of the other pixels are all “0”. As the coefficients aredivided by the prescribed divisor D and the remainder is rounded in thezigzag arrangement of the coefficients b₁-b₆₄ from the lower frequencyterm to the higher frequency term as mentioned above. The data of “0”pixels in the image data after the quantization shown in FIG. 11C iscompressible.

The compressed image data is processed in an opposite direction to aninverse quantized image data as shown in FIG. 12A, in other words, bymultiplying the divisor D used in the quantization for the image data inFIG. 11e. The obtained inverse quantized image data has restored coeffi-cients b′₁-b′₆₄ of pixels. Further, if the inverse quantized image datais transformed by an inverse DCT, a reproduced image composed of pixelsa′₁-a′₆₄ as shown in FIG. 12A which is almost the same as the originalpicture is obtained.

The second compressing method by means of the inter- frame correlationwill now be explained. In general, differ- ential data betweencorresponding pixels of frames adjacent in time sequence varies littlein comparison with raw data except when a picture changes to acompletely different picture. Therefore, if the differential data fromdata of pixels of the precedent frame is applied to the compressionmethod utilizing the intraframe correlation, the compressing effi-ciency is proved. Besides, when the differential data is expressed withthe use of variable length codes which is the third method to bedescribed below, the data can be com- pressed further.

The third compression method depending on an uneven distribution ofappearance probabilities of codes uses the VLC (variable length code).

In processing the MPEG standard data, the variable length codes areformed to be transmitted or recorded in a recording medium bycompressing moving picture data with the utilization of mainly theabove-mentioned three compres- sion methods. Therefore, it is necessaryto inversely process compressed data in order to reproduce data, inother words, to decompress the compressed data. That is to say, thecompressed data should be passed through a decoding process of thecompressed (encoded) variable length codes, an inverse quantization byadding differential data of the corresponding pixels between the framesand by multiplying the divisor used in the quantization, and the inverseDCT of the data obtained by the inverse quantization, etc. By theseprocesses, an image almost the same as the original picture isreproduced.

(4.2) Processing example of the MPEG standard moving picture data by theimage processing device of the invention.

Encoded data used in processing the MPEG standard data is roughlydivided into three kinds; system data relating to the operation of thedecoding system, video data, and audio data. Accordingly, it isnecessary to decode all three kinds of data in the decoding systemdecoding the whole MPEG standard data.

Considering loads impressed when the above three kinds of data aredecoded, the load at decoding of video data is extremely large whereasthe loads at decoding the other two kinds of data are extremely smaller.The video data includes original image data of blocks each comprising8×8 pixels, modification data of each block data, modification data forconstructing one frame by plural blocks, and the like addi- tional data.The load on decoding the additional data is extremely smaller than thaton decoding the block data.

From the above fact, in Embodiment 1 of the image processing device ofthe invention, data except the block data is decoded by the first andsecond microprocessors 10, 11 only by software. The first and secondmicroprocessors 10, 11, and the peripheral circuits cooperatively decodethe every block data of 8×8 pixels according to an algorithm shown in aflowchart of FIG. 13. The process in the flowchart will be now explainedin detail.

The variable-length-coded block data received through an externalantenna is input serially to the chip 1 of the image processing deviceof the invention through the serial signal line 27. The serial inputcircuit 18 converts the input data to parallel data of 32 bits each, andthe parallel data is written into the external memory 2 via the externalbus 21 to be buffered (S11).

The VLC decoder 14 reads the data written in the external memory 2 viathe external bus 21 (S12). The VLC decoder 14 further decodes the datato fixed length data in which one pixel is 8 bits (S13). The block datato be processed by the first microprocessor 10 among the decoded data bythe VLC decoder 14 is written in the high-speed memory 12. On the otherhand, the block data to be processed by the second microprocessor 11 iswritten in the high-speed memory 13.

The first microprocessor 10 reads the thus-decoded fixed length data perblock from the first high-speed memory 12, whereas the secondmicroprocessor 11 reads the decoded fixed length data from the secondhigh-speed memory 13. Then both microprocessors 10, 11 conduct theinverse quantization in parallel (S14). In the inverse quantizationprocess of the step S14, a block in a matrix wherein index values arearranged zigzag because each pixel data is mul- tiplied by two numbersis transformed to a block in a matrix wherein n (rows)×m (columns)pixels are arranged in the standard order to show an index value (8n+m).

The inverse quantized image data per block is stored in thegeneral-purpose registers 130 of the first and second microprocessors10, 11 to be used in the next inverse DCT process of the step S15. Inthe inverse DCT process of the step S15, two-dimensional blocks each of8×8 pixels which are in charge of the first and second microprocessors10, 11 are transformed at a high speed using a one-dimensional fastinverse 8-point DCT algorithm.

The description on the one-dimensional fast inverse DCT algorithm isgiven in detail in “Practical Fast I-DCT Algo- rithms with 11Multiplications,” (C. Loeffler, A. Ligtenberg, and G. Moschytz: Proc.Int'l Conf. on Acoustics, Speech, and Signal Processing 1989 (ICASSP'89), pp. 988-991).

In the next place, whether to add predictive data to the transformeddata is determined according to the modifica- tion data attached to theblock (S16). This determination depends on whether the currentlyprocessed block data is the differential data from the adjacent frame.Specifically, when the currently processed block data is thedifferential data from the adjacent frame, the predictive data isrequired to be added to the block data.

When it is determined to add the predictive data in the step S16, theblock loader 15 reads out data of the block to be predicted in theadjacent frame from the external memory 2 (S17). Then the block loader15 writes data of the subject block used by the first microprocessor 10to the first high- speed memory 12 and data of the block used by thesecond microprocessor 11 to the second high-speed memory 13,respectively.

In processing the MPEG standard moving picture data, the necessity ofaddition of the predictive data is indicated by the modification dataattached to every 6 chunks of block data. Accordingly, the block loader15 can start reading the block data to be predicted simultaneously withdecoding of each block data. In consequence of this, the block loader 15can read the predictive data in the step S17 in parallel with theinverse quantization in the step S14 and with the inverse DCT in thestep S15.

The first and second microprocessors 10, 11 read out the predictive datafrom the first and second high-speed memo- ries 12, 13, respectively.The first and second microproces- sors 10, 11 add the predictive data tothe respective data transformed by the inverse DCT (S18), then write theadded data to the external memory 2 as decoded data (S19).

On the contrary, when the predictive data is determined not to be addedto the block data in the step S16, the process is directly advanced tothe above-mentioned step S19. In this case, the first and secondmicroprocessors 10, 11 write the respective transformed data by theinverse DCT to the external memory 2 as the decoded data.

In the processes of the inverse quantization (S14), the inverse DCT(S15), and the addition of the predictive data (S18), the first andsecond microprocessors 10, 11 operate similarly though the handlingblock data are different. Therefore, both microprocessors 10, 11 canexecute the processes by handling instructions from the instructioncache 16 in parallel. In the process of writing the decoded data to theexternal memory 2 (S19), the microprocessors 10, 11 access the externalmemory 2 at a time different from each other to write data via theexternal bus 21.

The image data output circuit 17 reads out the decoded data written inthe external memory 2 by the frame and outputs the data outside throughthe bus 28 (S20). If the bus 28 is connected to an input line of animage display device, moving picture images are displayed on the imagedisplay device.

Among the above-mentioned processes shown in FIG. 13, the serial inputcircuit 18 executes the process in the step S11, the VLC decoder 14executes the processes in the steps S12, S13, the microprocessors 10, 11execute the processes in the steps S14, S15, S16, S18 and S19, and theimage data output circuit 17 executes the process in the step S20.

In order to process the MPEG standard moving picture data, four kinds ofhardware, namely, the serial input circuit 18, the VLC decoder 14, theblock loader 15, and the microprocessors 10, 11 operate in parallel tosuccessively process many chunks of block data on the basis of thepipeline processing, because each of as many as 5400 chunks of blockdata is composed of 64 pixels. Further, both microprocessors 10, 11transfer the block data between the processes in the steps S14-S16, S18,S19 through the general-purpose registers 130, thus eliminating anecessity for loads and stores of intermediate data of the processes.

(5) Effects

In above-mentioned Embodiment 1 fully described as above, four kinds ofhardware constructing the image pro- cessing device of the invention,that is, the VLC decoder 14, the block loader 15, and the twomicroprocessors 10, 11 cooperate to process the moving picture data,enabling high-speed processing. Specifically, the VLC decoder 14 decodesvariable length codes by hardware which is a process requiring a largequantity of data to be read out from the external memory 2 and difficultto carry out in parallel. The block loader 15 reads out the predictivedata from the external memory 2 by hardware which is large in quantity.The two microprocessors 10, 11 transform the data by software throughcomplicated processes, but in parallel.

The above-mentioned block loader 15 in Embodiment 1 is provided with theadder 176 as shown in FIG. 10, thereby to offer an adding function forpixel data. When the predictive data by the half pel is to be read fromthe external memory 2, the block loader 15 converts the read-out datacomprising 9 components in each row by adding the adjacent components,to block data comprising 8 components in each row. As a result, the VLCdecoder 14, the block loader 15, and the two microprocessors 10, 11 canprocess image data at a high speed and with a high efficiency even whenprocessing the predictive data by the half pel.

Further, in the above-mentioned Embodiment 1, the high-speed memories12, 13 for buffering intermediate processed data are provided betweenthe VLC decoder 14, the block loader 15, and the two microprocessors 10,11. Both the VLC decoder 14 and the block loader 15 can accordinglypreliminarily write data to be required in the future by the twomicroprocessors 10, 11 in the common high-speed memories 12, 13. Themicroprocessors 10, 11 can read out necessary data at any time from thehigh-speed memories 12, 13, respectively, at a high speed.

The block loader 15 in the above-mentioned Embodiment 1 has an extensionfunction of image data with zeros whereby 8-bit data output from theinput queue 171 is extended to 16-bit data with zeros by the adder 176,as shown in FIG. 10, and the extended data is written into the outputqueue 177. Accordingly, when the predictive data by the full pel is readout from the external memory 2, the block loader 15 transforms theread-out block data in which each component is 8 bits and one row iscomposed of 8 compo- nents to a block data of 8 components each of 16bits by extending each component to 16 bits with zeros, and writes theextended data into the high-speed memories 12, 13. Or, when reading outthe predictive data by the half pel from the external memory 2, theblock loader 15 transforms the read out block data consisting of 9components in each row, every component being 8 bits, to block data of 8components, each of 16 bits, by adding the adjacent components, andwrites the transformed data into the high-speed memories 12, 13.Therefore, both microprocessors 10, 11 can process image data at a highspeed and with a high efficiency because the processors process data inthe same format read from the high-speed memories 12, 13 both for thepredictive data by the half pel and for the predictive data by the fullpel.

Both of the microprocessors 10, 11 in the above-mentioned Embodiment 1read out the same instructions from the common instruction cache 16 inparallel thereby to execute the image processing program. Hence, bothmicroprocessors 10, 11 share a large portion of the program, so that anecessary storage capacity is reduced in comparison with a case wherethe two microprocessors 10, 11 have their own instruction caches.

[Embodiment 2]

(1) Entire architecture

FIG. 14 is a block diagram showing an example of the construction of asecond embodiment of the image process- ing device of the invention in asystem, to which a memory is connected. In the figure, numeral 5 denotesa chip on which is mounted the image processing device of the invention,which is connected to the external memory 2 composed of a plurality ofDRAM chips via the data bus 3, the address bus 4 and the like, similarto Embodiment 1.

The image processing device of Embodiment 2 is pro- vided with onemicroprocessor 30 instead of the micropro- cessors 10, 11 in Embodiment1 which has a processing speed twice as fast as that of themicroprocessors 10, 11. Therefore, one high-speed memory 12 issufficient in this embodiment. Further, an instruction cache 29exclusive for the microprocessor 30 is provided instead of the commoninstruction cache 16 in Embodiment 1 supplying instruc- tions to bothmicroprocessors 10, 11. The high-speed memory 12 and the microprocessor30 are connected by a bus 24.

Though two microprocessors 10,11 are used in the image processing deviceof Embodiment 1, one microprocessor 30 is enough so long as themicroprocessor 30 in the image processing device of this embodiment isat least twice as efficient as the microprocessor 10, 11. Accordingly,the two high-speed memories 12, 13 in the image processing device ofEmbodiment 1 may be replaced with one memory.

FIG. 15 is a block diagram showing the entire architecture of themicroprocessor 30 in the second embodiment of the image processingdevice of the invention. In the embodiment, the instruction set and theconstruction of registers of the microprocessor 30 are similar to thosein the microprocessors 10, 11 in Embodiment 1.

A difference in the microprocessor 30 of the image processing device ofEmbodiment 2 from the microproces- sor 10(11) of Embodiment 1 is aconnection between the bus interface circuit 163 and the instructionfetch unit 161. The instruction fetch unit 161 in the microprocessor 30deter- mines to access whether the instruction cache 29 or the externalmemory 2 via the bus interface circuit 163 in compliance with aninstruction address, thereby to fetch an instruction from theinstruction cache 29 or from the exter- nal memory 2. Accordingly, theinstruction fetch unit 161 has a direct route for reading an instructionfrom the instruction cache 29 whereas the bus interface circuit 163 hasno such route for reading an instruction from the instruction cache 29.

(2) Processing example of the MPEG standard moving picture data

When the image processing device of Embodiment 2 processes the MPEGstandard moving picture data, pro- cesses are similar to those inEmbodiment 1 except a process of decoding block data of 8×8 pixels each.However, even the decoding process is basically the same as inEmbodiment 1 shown in FIG. 13. A sole difference is that one micropro-cessor 30 in place of the two microprocessors 10, 11 in Embodiment 1executes the processes in the steps S14, S15, S16, S18 and S19 inEmbodiment 2.

(3) Effects

In the above-mentioned Embodiment 2, three kinds of hardware consistingthe image processing device of the invention, that is, the VLC decoder14, the block loader 15, and the microprocessor 30 cooperate to processmoving picture data, realizing high-speed processing. Specifically, theVLC decoder 14 decodes variable length codes by hardware which requiresreading of a large amount of data from the external memory 2 and is hardto execute in parallel. The block loader 15 reads out the predictivedata from the external memory 2 by hardware, although the predictivedata is of a large quantity. The microprocessor 30 transforms the databy software.

Further, in the above-mentioned Embodiment 2, the high-speed memory 12for buffering intermediate processed data is provided between the VLCdecoder 14 and the block loader 15, and the microprocessor 30. As aresult, the VLC decoder 14 and the block loader 15 can preliminarilywrite data to be required by the microprocessor 30 in the high-speedmemory 12. Accordingly, the microprocessor 30 can read out necessarydata at any time from the high-speed memory 12 at a high speed.

At the same time, the construction of the above-mentioned block loader15 in Embodiment 2 is the same as in Embodiment 1 shown in FIG. 10.Hence, needless to say, the block loader 15 has the adding function ofpixel data and the extension function of pixel data with zeros similarto in Embodiment 1, with the same effects exerted as in Embodi- ment 1.

[Embodiment 3]

(1) Entire architecture

FIG. 16 is a block diagram showing an example of the construction of athird embodiment of the image processing device of the invention in asystem, to which is connected a memory. In the figure, numeral 6 denotesa chip on which is mounted the image processing device of the invention,which is connected to the external memory 2 composed of a plurality ofDRAM chips via the data bus 3, the address bus 4 and the like, similarto the embodiments mentioned earlier.

The image processing device of the invention in this embodiment has theconstruction in which the block loader 15 is removed from the secondembodiment of the image processing device shown in FIG. 14. Therefore,though it is necessary for the microprocessor 30 of the image processingdevice in this embodiment to directly read out the predictive data fromthe external memory 2, which requires a faster speed than that of themicroprocessor 30 in Embodiment 2, an amount of hardware required by theblock loader 15 is eliminated. However, the microprocessor 30 reads outthe predictive data from the external memory 2 by software, andtherefore no additional function is never necessitated in themicroprocessor 30.

(2) Processing example of the MPEG standard moving picture data

When the image processing device of Embodiment 3 processes the MPEGstandard moving picture data, pro- cesses are similar to those inEmbodiment 1 except a process of decoding every block data of 8×8pixels. Even the process of decoding is basically the same as inEmbodiment 1 shown in FIG. 13. Differences are that one microprocessor30 in Embodiment 3 instead of the two microprocessors 10, 11 inEmbodiment 1 executes the processes in the steps S14, S15, S16, S18 andS19 of FIG. 13, and that the microprocessor 30 also executes the processin the step S17 by software although the process is executed by theblock loader 15 by hardware in Embodiment 3.

(3) Effects

In the above-mentioned Embodiment 3, two kinds of hardware constructingthe image processing device of the invention, that is, the VLC decoder14 and the micropro- cessor 30 cooperate operate to process movingpicture data, thereby achieving a high speed. Specifically, the VLCdecoder 14 decodes variable length codes by hardware, which is a processrequiring a large amount of data to be read out from the external memory2 and hard to perform in parallel. The microprocessor 30 transforms thedata and reads out the predictive data from the external memory 2 bysoftware.

Further, in the above-mentioned Embodiment 3, the high-speed memory 12for buffering intermediate processed data is provided between the VLCdecoder 14 and the micropro- cessor 30. As a result, the VLC decoder 14can preliminarily write data to be necessitated by the microprocessor 30in the high-speed memory 12. Accordingly, the microprocessor 30 can readout necessary data at any time from the high-speed memory 12 at a highspeed.

[Embodiment 4]

(1) Entire architecture

FIG. 17 is a block diagram showing an example of the construction of afourth embodiment of the image process- ing device of the invention in asystem, to which is con- nected a memory. In the figure, numeral 7denotes a chip on which is mounted the image processing device of theinvention, which is connected to the external memory 2 composed of aplurality of DRAM chips via the data bus 3, the address bus 4 and thelike, similar to the embodiments stated earlier.

The image processing device of the invention in this embodiment has theconstruction in which the VLC decoder 14 is removed from the secondembodiment of the image processing device shown in FIG. 14. Therefore,though the microprocessor 30 of the image processing device in thisembodiment is required to directly read out the variable length codesfrom the external memory 2 and to decode the variable length codes todata of fixed length codes, which necessitates a processing speed fasterthan that of the microprocessor 30 in Embodiment 2, an amount ofhardware required by the VLC decoder 14 is eliminated. However, themicroprocessor 30 decodes the variable length codes by software, and nofunction is to be added to the micropro- cessor 30.

(2) Processing example of the MPEG standard moving picture data

When the image processing device of Embodiment 4 processes the MPEGstandard moving picture data, pro- cesses are similar to those inEmbodiment 1 except a process of decoding every block data of 8×8pixels. Even the process of decoding is basically the same as inEmbodiment 1 shown in FIG. 13. Differences are that one microprocessor30 instead of the two microprocessors 10, 11 executes the processes inthe steps S14, S15, S16, S18 and S19 of FIG. 13, and that themicroprocessor 30 also executes both processes in the steps S12 and S13by software instead of by the VLC decoder 14 by hardware.

(3) Effects

In the above-mentioned Embodiment 4, two kinds of hardware constructingthe image processing device of the invention, that is, the block loader15 and the microproces- sor 30 cooperatively process moving picture dataat a high speed. Specifically, the block loader 15 reads out the pre-dictive data from the external memory 2 by hardware, which requiresreading of a large amount of data. The micropro- cessor 30 transformsthe data and decodes variable length codes by software.

Further, in the above-mentioned Embodiment 4, the high-speed memory 12for buffering intermediate processed data is provided between the blockloader 15 and the micropro- cessor 30. As a result, the block loader 15can preliminarily write data to be necessitated by the microprocessor 30in the high-speed memory 12. Accordingly, the microprocessor 30 can readout necessary data at any time from the high-speed memory 12 at a highspeed.

Besides, the construction of the above-mentioned block loader 15 inEmbodiment 4 is the same as in Embodiment 1 shown in FIG. 10. It isneedless to say that the block loader 15 has the adding function ofpixel data and the extension function of pixel data with zeros, similarto Embodiment 1, with effects also similar to Embodiment 1.

[Embodiment 5]

(1) Entire architecture

FIG. 18 is a block diagram showing an example of the construction of afifth embodiment of the image processing device of the invention in asystem, to which a memory is connected. In the figure, numeral 8 denotesa chip on which is mounted the image processing device of the inventionwhich is connected to the external memory 2 composed of a plurality ofDRAM chips via the data bus 3, the address bus 4 and the like, similarto the foregoing embodiments.

The image processing device of Embodiment 5 has the construction inwhich the instruction cache 16 in the first embodiment of the imageprocessing device in FIG. 1 is replaced with an instruction ROM 31. Theinstruction ROM 31 stores portions of the program executed by the firstand second microprocessors 10, 11, e.g., processes in the steps S14,S15, S16, S18 and S19 shown in FIG. 13 which are especially necessary toprocess at a high speed. The instruc- tion ROM 31 can supply either oneof the first and second microprocessors 10, 11 with the instruction orcan supply both microprocessors 10, 11 with the same instruction inparallel. Both of the microprocessors 10, 11 fetch instruc- tions fromthe external memory 2 as well as from the instruction ROM 31 and executethe instructions.

Both microprocessors 10, 11 of the image processing device of Embodiment5 have the same construction as in Embodiment 1 shown in FIG. 8 except aconnection of the bus interface circuit 163 with the outside. Theinstruction set and the construction of registers are similar to thosein the above-mentioned Embodiment 1. A difference is that the businterface circuit 163 is connected to the external bus 21, to the firsthigh-speed memory 12 and to the instruction ROM 31 as a result of thereplacement of the instruction cache 16 with the instruction ROM 31.Accordingly, the bus interface circuit 163 determines to access theinstruction ROM 31 or the external memory 2 according to an instructionaddress, thereby to fetch the instruction from either the instructionROM 31 or the external memory 2.

(2) Processing example of the MPEG standard moving picture data

When the image processing device of Embodiment 5 processes the MPEGstandard moving picture data, pro- cesses are similar to those inEmbodiment 1 except a process of decoding every block data of 8×8pixels. Even the process of decoding is basically the same as inEmbodiment 1. A difference is that both microprocessors 10, 11 fetch aninstruction from either of the instruction ROM 31 and the externalmemory 2 according to the instruction address. The microprocessors 10,11 execute the same instructions sup- plied from the instruction ROM 31in parallel in the steps S14, S15, S16 and S18 of FIG. 13.

(3) Effects

In this embodiment, the two microprocessors 10, 11 read out the sameinstructions in parallel from the common instruction ROM 31 thereby toexecute the image processing program. Hence, both microprocessors 10, 11can share a large portion of the image processing program thereby toreduce a storage capacity in comparison with a case where the twomicroprocessors 10, 11 have their own instruction ROMs.

[Embodiment 6]

(1) Entire architecture

FIG. 19 is a block diagram showing an example of the construction of asixth embodiment of the image processing device of the invention in asystem, to which is connected a memory. In the figure, numeral 9 denotesa chip on which is mounted the image processing device of the invention,which is connected to the external memory 2 composed of plurality ofDRAM chips via the data bus 3, the address bus 4 and the like, similarto the embodiments described above.

The image processing device in Embodiment 6 has the construction inwhich the instruction cache 29 in the image processing device ofEmbodiment 2 is replaced with an instruction ROM 32. The instruction ROM32 stores por- tions of the program executed by the microprocessor 30,such as processes in the steps S14, S15, S16, S18 and S19 shown in FIG.13 which are especially necessary to process at a high speed. Themicroprocessor 30 fetches an instruc- tion from either the instructionROM 32 or the external memory 2 and executes the instruction.

The microprocessor 30 of the image processing device of Embodiment 6 hasthe same construction as in Embodiment 2 shown in FIG. 15 except aconnection of the instruction fetch unit 161. The instruction set andthe construction of registers are similar to those in theabove-mentioned Embodiment 2. A difference is that the instruction fetchunit 161 is connected to the instruction ROM 32, not to the instructioncache 29 as a result of the replacement of the instruction cache 16 withthe instruction ROM 32. Accordingly, the instruction fetch unit 161determines to access the instruction ROM 32 or the external memory 2 viathe bus interface circuit 163 according to an instruction address,thereby to fetch the instruction from either the instruction ROM 32 orthe external memory 2.

(2) Processing example of the MPEG standard moving picture data

When the image processing device of Embodiment 6 processes the MPEGstandard moving picture data, pro- cesses are totally the same as thosein Embodiment 1 except a process of decoding 8×8 pixel block data. Eventhe process of decoding is basically the same as in Embodiment 1 shownin FIG. 13. Differences are that one microprocessor 30 instead of twomicroprocessors 10, 11 executes the pro- cesses in the steps S14, S15,S16, S18 and S19 of FIG. 13, and that the microprocessor 30 fetches aninstruction from either the instruction ROM 32 or the external memory 2according to the instruction address.

(3) Effects

In this embodiment, the microprocessor 30 reads out the instructionespecially necessary to process at a high speed from the instruction ROM32 having a larger storage capac- ity per unit area than the instructioncache and having an access speed equivalent to that of the instructioncache to execute the image processing program. Therefore, the real- izedimage processing device occupies a smaller area on the chip incomparison with a device using the instruction cache.

[Embodiment 7]

(1) Entire architecture

FIG. 20 is a block diagram showing an example of the construction of aseventh embodiment of the image process- ing device of the invention ina system, to which is con- nected a memory. In the figure, numeral 35denotes a chip on which is mounted the image processing device of theinvention, which is connected to the external memory 2 composed of aplurality of DRAM chips via the data bus 3, the address bus 4 and thelike, similar to the embodiments mentioned earlier.

The image processing device of Embodiment 7 has the construction inwhich a memory 33 is added to the above-mentioned image processingdevice of Embodiment 6 shown in FIG. 19, with a bus 34 for inputting asignal output from the memory 33 to the VLC decoder 14. In the device,the memory 33 buffers variable length code data which is an outputsignal from the serial input circuit 18, and the VLC decoder 14 readsout the buffered data from the memory 33 via the bus 34. That is, thevariable length code signal input into the image processing device onthe chip 35 through the serial input circuit 18 is buffered in thememory 33, not in the external memory 2.

(2) Processing example of the MPEG standard moving picture data

The image processing device of Embodiment 7 processes the MPEG standardmoving picture data in almost the same way as in the above-mentionedEmbodiment 6. Differences are that the variable length codes are writteninto the memory 33, not in the external memory 2 in the processcorresponding to that in the step S11 of FIG. 13, and that the variablelength codes are read out from the memory 33, not from the externalmemory 2 in the process corresponding to that in the step S12 of FIG.13.

(3) Effects

The device of Embodiment 7 is provided with the spe- cialized memory 33for buffering the variable length codes, which eliminates the necessityfor the serial input circuit 18 and the VLC decoder 14 to access theexternal memory 2. Accordingly, controlling of the access right to theexternal memory 2 via the external bus 21 becomes simpler in comparisonwith Embodiment 6.

[Embodiment 8]

(1) Entire architecture

FIG. 21 is a block diagram showing an example of the construction of aneighth embodiment of the image process- ing device of the invention in asystem, to which is con- nected a memory. In the figure, numeral 36denotes a chip on which is mounted the image processing device of theinvention which is connected to the external memory 2 composed of aplurality of DRAM chips via the data bus 3, the address bus 4 and thelike, similar to the embodiments mentioned earlier.

The image processing device of Embodiment 8 mounted on the chip 36 hasthe construction in which the same memory 33 and bus 34 as in theabove-mentioned Embodi- ment 7 are added to the image processing deviceof Embodi- ment 4 having no VLC decoder 14 of FIG. 17. In the device ofEmbodiment 8, the bus 34 directly connects the memory 33 and themicroprocessor 30. Specifically, the memory 33 buffers the variablelength code data output from the serial input circuit 18, then themicroprocessor 30 directly reads out the buffered data from the memory33 through the bus 34.

(2) Processing example of the MPEG standard moving picture data

The image processing device of Embodiment 8 processes the MPEG standardmoving picture data in almost the same way as in the above-mentionedEmbodiment 4. Differences are that the variable length codes are writteninto the memory 33, not into the external memory 2 in the processcorresponding to that in the step S11 of FIG. 13, and that the variablelength codes are read out from the memory 33 instead of from theexternal memory 2 in the process corresponding to that in the step S12of FIG. 13.

(3) Effects

The device of Embodiment 8 is provided with the spe- cialized memory 33for buffering the variable length codes, which makes it unnecessary forthe serial input circuit 18 to access the external memory 2.Accordingly, controlling of the access right to the external memory 2via the external bus 21 becomes simpler in comparison with Embodiment 4.

(1) Entire architecture

[Embodiment 9]

FIG. 22 is a block diagram showing an example of the construction of aninth embodiment of the image processing device of the invention in asystem, to which is connected a memory. In the figure, numeral 40denotes a chip on which is mounted the image processing device of theinvention, which is connected to the external memory 2 composed of aplurality of DRAM chips via the data bus 3, the address bus 4 and thelike, similar to the embodiments mentioned earlier.

The image processing device of Embodiment 9 is pro- vided with ahigh-speed memory 37 specialized for the VLC decoder 14 in addition tothe high-speed memory 12 pro- vided in the image processing device ofEmbodiment 6 shown in FIG. 19. The VLC decoder 14 is connected to thehigh-speed memory 37 via a bus 39. The high-speed memory 37 is connectedto the microprocessor 30 via a bus 38. Therefore, the VLC decoder 14 andthe block loader 15 can respectively transfer data to the microprocessor30 via the high-speed memories 37 and 12. In the device, the VLC decoder14 decodes the variable length codes fetched from the external memory 2into fixed length code data of 8 bits per pixel and writes the decodeddata into the high-speed memory 37 through the bus 39. Meanwhile, themicropro- cessor 30 reads out the fixed length code data from thehigh-speed memory 37 through the bus 38. The block loader 15 reads outthe predictive data from the external memory 2, then writes the read-outdata into the high-speed memory 12 through the internal bus 20. Themicroprocessor 30 reads out the predictive data from the memory 12through the bus 24.

(2) Processing example of the MPEG standard moving picture data

The image processing device of Embodiment 9 processes the MPEG standardmoving picture data in almost the same way as in the above-mentionedEmbodiment 6. Differences are that the VLC decoder 14 and the blockloader 15 write the results of the processes corresponding to those inthe steps S13 and S17 of FIG. 13 in the independent high-speed memories37 and 12, respectively, and the microprocessor 30 reads the result datafrom the high-speed memories 37 and 12 in the processes corresponding tothose in the steps S14 and S18 of FIG. 13.

(3) Effects

In the device of Embodiment 9, the VLC decoder 14 and the block loader15 transfers data to the microprocessor 30 through the independenthigh-speed memories 37 and 12, respectively, so that the VLC decoder 14and the block loader 15 can write data into the high-speed memories 37and 12 without controlling of the access right to the internal bus 20taken into consideration although it is necessary in the imageprocessing device of Embodiment 6. Accordingly, controlling of writingto the high-speed memories 12, 37 is facilitated.

[Other Embodiments]

Though the VLC decoder 14 or the block loader 15 transfers data to themicroprocessor 10, 11 or to the micro- processor 30 through thehigh-speed memory 12 or 13 in the abovementioned Embodiments 1-9, movingpicture data is similarly processable without the high-speed memories12, 13 if the microprocessor has a function of prefetching data toregisters.

Further, though the block loader 15 extends an 8 bit pixel value to a 16bit pixel value with zeros when processing the predictive data by thefull pel in all of the abovementioned Embodiments 1-9 except Embodiment3, the block loader 15 may write the 8-bit pixel value read out from theexternal memory 2 as it is without an extension to the high-speed memory12 or 13 in case of processing the predictive data by the full pel.

Besides, though the block loader 15 adds adjacent pixel values in thesame row when loading block data in all of the above-mentionedEmbodiments 1-9 except Embodiment 3, the block loader 15 may be adaptedto add pixel values of adjacent rows or add neighboring four pixelvalues by setting a register holding entire pixel data of one rowthereby to provide a function to add pixel values of adjacent rows whenloading the block data.

Further, though the microprocessors 10, 11 or the micro- processor 30fetches and executes an instruction from the instruction ROMs 31, 32 orthe external memory 2 in all of the above-mentioned Embodiments 5-7, 9,the micropro- cessors 10, 11 or the microprocessor 30 is not required tofetch an instruction from the external memory 2 if the instruction ROMs31, 32 can store the entire program necessary for the image processing.

Moreover, though variable length code data is input through the serialsignal line 27 and the processed data is output to the external displayunit through the bus 28 in all of the above-mentioned Embodiments 1-6,the serial input circuit 18 and the image data output circuit 17 may beomitted if the variable length coded data preliminarily stored in theexternal memory 2 is processed and written back to the external memory2.

Further, the DRAM controller 19 in all of Embodiments is unnecessary ifthe external memory 2 includes a DRAM controller or if the externalmemory 2 is composed of a memory other than DRAM.

As this invention may be embodied in several forms without departingfrom the spirit of essential characteristics thereof, the presentembodiments are therefore illustrative and not restrictive, since thescope of the invention is defined by the appended claims rather than bythe description preceding them, and all changes that fall within metesand bounds of the claims, or equivalence of such metes and boundsthereof are therefore intended to be embraced by the claims.

1. An image processing device comprising: a processor which includes aninstruction decoder for decoding instructions of an image processingprogram and an instruction executing unit for executing the instructionsresponsive to outputs from said instruction decoder, and outputs theexecution result by said instruction executing unit; and a data loader,connected to said processor, which includes a data reading unit forreading image data of fixed length codes, an adding unit, connected tothe data reading unit, for adding image data of at least two adjacentpixels of the image data read by the data reading unit, and a datawriting unit, connected to the adding unit, for writing the additionresult by the adding unit into said processor, wherein said processor isconfigured to perform a process of decoding a first kind of image dataof variable length codes to a second kind of image data of fixed lengthcodes, a process of transforming the second kind of image data to athird kind of image data, a process of performing a prescribed operationbetween the third kind of image data and the addition result written bysaid data loader.
 2. An image processing device comprising: a memory forstoring data used for executing an image processmg program; a processor,connected to said memory, which includes an instruction decoder fordecoding instructions of the image processing program and an instructionexecuting unit for executing the instructions responsive to outputs fromsaid instruction decoder, and performs a pre- scribed operationaccording to the instructions described in the image processing programand outputs the operation result; and a data loader, connected to saidmemory, which includes a data reading unit for reading image data offixed length codes, an adding unit, connected to the data reading unit,for adding image data of at least two adjacent pixels read by the datareading unit, and a data writing unit, connected to the adding unit, forwriting the addition result by the adding unit into said memory, whereinsaid processor is configured to perform a process of decoding a firstkind of image data of variable length codes to a second kind of imagedata of fixed length codes, a process of transforming the sec- ond kindof image data to a third kind of image data, a process of performing aprescribed operation between the third kind of image data and theaddition result written by said data loader into said memory.
 3. Animage processing device comprising: a memory for storing data used forexecuting an image processmg program; a processor, connected to saidmemory, which includes an instruction decoder for decoding instructionsof the image processing program and an instruction executing unit forexecuting the instructions responsive to outputs from said instructiondecoder, and performs a pre- scribed operation according to theinstructions described in the image processing program and outputs theoperation result; and a data loader, connected to said memory, whichincludes a data reading unit for reading image data of fixed lengthcodes for the half pel or for the full pel, an adding unit, connected tothe data reading unit, for adding image data of at least two adjacentpixels of the image data of fixed length codes read by the data readingunit in case of processing of image data for the half pel, whileextending a bit width of the image data of fixed length codes read bythe reading unit in case of processing of image data for the full pel,and a data writing unit, connected to the adding unit, for writing tosaid memory first data of the addition result by the adding unit orsecond data extended in the bit width by the adding unit, wherein saidprocessor is configured to perform a process of decoding a first kind ofimage data of variable length codes to a second kind of image data offixed length codes, a process of transforming the second kind of imagedata to a third kind of image data, a process of performing a prescribedoperation between the third kind of image data and the first or seconddata by reading the first data from said memory in case of processing ofthe image data for the half pel or the second data from said memory incase of processing of the image data for the full pel.
 4. An imageprocessing device comprising: a first memory and a second memory forstoring data used for executing an image processing program; a firstprocessor, connected to the first memory, which includes a firstinstruction decoder for decoding instructions of the image processingprogram, and a first instruction executing unit for executing theinstruc- tions responsive to outputs from the first instruction decoder,and outputs the execution result by the first instruction executingunit; a second processor, connected to the second memory, which includesa second instruction decoder for decod- ing the instructions of theimage processing program and a second instruction executing unit forexecuting the instructions responsive to outputs from the secondinstruction decoder, and outputs the execution result by the secondinstruction executing unit; a variable length code decoder, connected tothe first and second memories, which decodes a first kind of image dataof variable length codes to a second kind of image data of fixed lengthcodes and outputs the decoding result to the first or second memory; anda data loader, connected to the first and second memories, which outputsimage data of fixed length codes to the first or second memory, whereinsaid first and second processors respectively are configured to performa process of reading the second kind of image data from the first orsecond memory and transforming the second kind of image data to a thirdkind of image data, and a process of reading image data of fixed lengthcodes from said first or second memory and performing a prescribedoperation between the third kind of image data and the image data of thefixed length codes.
 5. An image processing device as set forth in claim4, further comprising a third memory, connected to the first and secondprocessors, for storing instructions of the image processing program,wherein the first and second processors further include, respectively,means for operating in parallel with each other by reading out theinstructions from the third memory.
 6. An image processing devicecomprising: a processor which includes an instruction decoder fordecoding instructions of the image processing program and an instructionexecuting unit for executing the instructions responsive to outputs fromsaid instruction decoder, and outputs the execution result by saidinstruction executing unit; a variable length code decoder, connected tosaid processor, which decodes a first kind of image data of variablelength codes to a second kind of image data of fixed length codes andoutputs the second kind of image data to said processor; and a dataloader, connected to said processor, which includes a data reading unitfor reading image data of fixed length codes, an adding unit, connectedto the data reading unit, for adding image data of at least two adjacentpixels of the image data of fixed length codes, and a data writing unit,connected to the adding unit, for writing the addition result by theadding unit into said processor, wherein said processor is configured toperform a process of transforming the second kind of image data outputfrom said variable length code decoder to a third kind of image data,and a process of performing a prescribed operation between the thirdkind of image data and the addition result written by said data loader.7. An image processing device comprising: a memory for storing data usedfor executing an image processmg program; a processor, connected to saidmemory, which includes an instruction decoder for decoding instructionsof the image processing program and an instruction executing unit forexecuting the instructions responsive to outputs from said instructiondecoder, and outputs and execu- tion result by said instructionexecuting unit; a variable length code decoder, connected to saidmemory, which decodes a first kind of image data of variable lengthcodes to a second kind of image data of fixed length codes and outputsthe second kind of image data to said memory; and a data loader,connected to said memory, which includes a data reading unit for readingimage data of fixed length codes, an adding unit, connected to the datareading unit, for adding image data of at least two adjacent pixels ofthe image data of fixed length codes read by the data reading unit, anda data writing unit connected to the adding unit, for writing theaddition result by the adding unit into said memory, wherein saidprocessor is configured to perform a process of reading the second kindof image data from said memory and transforming the second kind of imagedata to a third kind of image data, and a process of performing aprescribed operation between the third kind of image data and theaddition result read from said memory.
 8. An image processing devicecomprising: a first and second memories for storing data used forexecuting an image processing program; a processor, connected to thefirst memory, which includes an instruction decoder for decodinginstructions of the image processing program and a first instructionexecuting unit for executing the instructions responsive to outputs fromthe first instruction decoder, and out- puts the execution result by thefirst instruction execut- ing unit; a second processor, connected to thesecond memory, which includes a second instruction decoder for decod-ing the instructions of the image processing program and a secondinstruction executing unit for executing the instructions responsive tooutputs from the second instruction decoder, and outputs the executionresult by the second instruction executing unit; a variable length codedecoder, connected to the first and second memories, which decodes afirst kind of image data of variable length codes to a second kind ofimage data of fixed length codes and outputs the decoding result to thefirst and second memory; a data loader, connected to the first andsecond memories, which includes a data reading unit for reading imagedata of fixed length codes, an adding unit, connected to the datareading unit, for adding image data of at least two adjacent pixels ofthe image data of fixed length codes read by the data reading unit, anda data writing unit connected to the adding unit, for writing theaddition result by the adding unit to the first and second memory,wherein said first and second processors respectively is configured toperform a process of reading the second kind of image data from thefirst or second memory and transforming the second kind of image data toa third kind of image data, and a process of reading the addition resultfrom said first or second memory and performing a prescribed operationbetween the third kind of image data and the addition result.
 9. Animage processing device as set forth in claim 8, further comprising athird memory, connected to the first and second processors, for storinginstructions of the image processing program, wherein the first andsecond processors further include, respectively, means for operating inparallel with each other by reading out the instructions from the thirdmemory.
 10. An image processing device comprising: a memory for storingdata used for executing an image processmg program; a read-only memoryfor storing the image processing program; a processor, connected to saidmemory and said read only memory, which includes an instruction decoderfor decoding instructions of the image processing program and aninstruction executing unit for executing the instructions responsive tooutputs from said instruction decoder, and outputs the execution resultby said instruction executing unit; a variable length code decoder,connected to said memory, which decodes a first kind of image data ofvariable length codes to a second kind of image data of fixed lengthcodes and outputs the second kind of image data to said memory; and adata loader, connected to said memory, which includes an adding unitthat adds image data of at least two adj acent pixels read by the dataloader and outputs image data of fixed length codes to said memory,wherein said processor is configured to perform a process of reading thesecond kind of image data from said memory and transforming the secondkind of image data to a third kind of image data, and a process ofreading image data of fixed length codes from said memory and performinga prescribed operation between the third kind of image data and theimage data of fixed length codes.
 11. An image processing devicecomprising: first and second memories for storing data used forexecuting an image processing program; a processor, connected to thefirst and second memories, which includes an instruction decoder fordecoding instructions of the image processing program and an instructionexecuting unit for executing the instructions responsive to outputs fromsaid instruction decoder, and outputs the execution result by saidinstruction executing unit; a variable length code decoder, connected tothe first memory, which decodes a first kind of image data of variablelength codes to a second kind of image data of fixed length codes andoutputs the second kind of image data to the first memory; and a dataloader, connected to the second memory, which includes an adding unitthat adds image data of at least two adjacent pixels read by the dataloader and outputs image data of fixed length codes to the secondmemory, wherein said processor is configured to perform a process ofreading the second kind of image data from the first memory andtransforming a second kind of image data to a third kind of image data,and a process of reading image data of fixed length codes from thesecond memory and performing a prescribed operation between the thirdkind of image data and the image data of fixed length codes.
 12. Animage processing device comprising: a processor which includes aninstruction decoder for decoding instructions of an image processingprogram and an instruction executing unit for for executing theinstructions responsive to outputs for from said instruction decoder,and outputs the execution result by said instruction executing unit; anda variable length code decoder, connected to said processor, whichdecodes a first kind of image data of variable length codes to a secondkind of image data of fixed length codes, and outputs the second kind ofdata to said processor, wherein said processor is configured to performa process of transforming the second kind of image data output from saidvariable length code decoder to a third kind of image data according tothe image processing program, and wherein the processor includes aregister having a first portion and a second portion for storing twoimage data each comprising a number (n) of bits, and the instructionexecuting unit of the processor is able to independently access saidfirst portion and said second portion of said register.
 13. An imageprocessing device comprising: a processor which includes an instructiondecoder for decoding instructions of an image processing program and aninstruction executing unit for executing the instructions responsive tooutputs from said instruction decoder, and outputs the execution resultby said instruction executing unit; and a data loader, connected to saidprocessor, which outputs image data for fixed length codes to saidprocessor, wherein said processor is configured to perform a process ofdecoding a first kind of image data of variable length codes to a secondkind of image data of fixed length codes, a process of transforming thesecond kind of image data to a third kind of image data, and a processof a prescribed operation between the third kind of image data and theimage data of fixed length codes output from said data loader, andwherein the processor includes a register having a first portion and asecond portion for storing two image data each comprising a number (n)of bits, and the instruction executing unit of the processor is able toindependently access said first portion and said second portion of saidregister.
 14. An image processing device comprising: a processor whichincludes an instruction decoder for decoding instructions of an imageprocessing program and an instruction executing unit for for executingthe instructions responsive to outputs for from said instructiondecoder, and outputs the execution result by said instruction executingunit; and a variable length code decoder, connected to said processor,which decodes a first kind of image data of variable length codes to asecond kind of image data of fixed length codes, and outputs the secondkind of data to said processor, wherein said processor is configured toperform a process of transforming the second kind of image data outputfrom said variable length code decoder to a third kind of image dataaccording to the image processing program, and wherein each of theinstructions decoded by the instruction decoder of the processorincludes a first operation specifying field and a second operationspeci- fying field each for specifying an operation, and the instructionexecuting unit of the processor has a first operation unit and a secondoperation unit for perform- ing said operations specified by said firstand second operation specifying fields in parallel.
 15. An imageprocessing device comprising: a processor which includes an instructiondecoder for decoding instructions of an image processing program and aninstruction executing unit for executing the instructions responsive tooutputs from said instruction decoder, and outputs the execution resultby said instruction executing unit; and a data loader, connected to saidprocessor, which outputs image data for fixed length codes to saidprocessor, wherein said processor is configured to perform a process ofdecoding a first kind of image data of variable length codes to a secondkind of image data of fixed length codes, a process of transforming thesecond kind of image data to a third kind of image data, and a processof a prescribed operation between the third kind of image data and theimage data of fixed length codes output from said data loader, andwherein each of the instructions decoded by the instruc- tion decoder ofthe processor includes a first operation specifying field and a secondoperation specifying field each for specifying an operation, and theinstruction executing unit of the processor has a first operation unitand a second operation unit for performing said opera- tions specifiedby said first and second operation speci- fying fields in parallel. 16.An image processing device comprising: a processor, connected to amemory, which includes an instruction decoder for decoding instructionsof an image processing program and an instruction executing unit forexecuting the instructions responsive to outputs from said instructiondecoder, and outputs the execution result by said instruction executingunit; and a variable length code decoder, connected to the memory, whichdecodes a first kind of image data of variable length codes to a secondkind of image data of fixed length codes, and provides the second kindof image data to the memory, wherein said processor is configured toperform a process of reading the second kind of image data from thememory and transforming the second kind of image data a to a third kindof image data according to the image processing program, and wherein theinstructions decoded by the instruction decoder of the processorincludes at least an instruction having a first operation specifyingfield and a second operation specifying field each for specifying anoperation, and the instruction executing unit of the processor has afirst operation unit and a second operation unit for performing saidoperations specified by said first and second operation specifyingfields in parallel.
 17. The image processor device as set forth in claim14, further comprising a data loader loading data from a memory andoutputting image data of fixed length codes; wherein said processor isconfigured to further perform a process of operating between the thirdkind of image data and the image data of fixed length codes output fromthe data loader.
 18. The image processor device as set forth in claim16, further comprising: a data loader loading data from another memoryand outputting image data of fixed length codes; wherein said processoris configured to further perform a process of operating between thethird kind of image data and the image data of fixed length codes outputfrom the data loader.
 19. An image processing device comprising: aprocessor, connected to a memory, which includes an instruction decoderfor decoding instructions of an image processing program and aninstruction executing unit for executing the instructions responsive tooutputs from said instruction decoder, and outputs the execution resultby said instruction executing unit; and a data loader, connected to thememory, which outputs image data for fixed length data to the memory,wherein said processor is configured to perform a process of decoding afirst kind of image data of variable length codes to a second kind ofimage data, of fixed lengthscodes, a process of transforming the secondkind of image data to a third kind of image data and a process of aprescribed operation between the third kind of image data and the imagedata of fixed length codes output from the memory, and wherein each ofthe instructions decoded by the instruction decoder of the processorincludes a first operation specifying field and a second operationspecifying field each for specifying an operation, and the instructionexecuting unit of the processor has a first operation unit and a secondoperation unit for the processor for performing said operationsspecified by said first and second operation specifying fields inparallel.
 20. An image processing device comprising: a processor whichincludes an instruction decoder for decoding instructions of an imageprocessing program and an instruction executing unit for executing theinstructions responsive to outputs from said instruction decoder; and avariable length code decoder, which decodes a first kind of image dataof variable length codes to a second kind of image data of fixed lengthcodes, and outputs the second kind of data, wherein said processor isconfigured to perform a process of transforming the second kind of imagedata output from said variable length code decoder to a third kind ofimage data according to the image processing program, and wherein theprocessor further includes a plurality of registers storing image data,each register having a plurality of portions, said instruction executingunit executes a prescribed instruction decoded by said instructiondecoder, the prescribed instruction having a first field specifyingcontents of an operation, a second field specifying a register number ofeach of said plurality of registers, and a third field specifying eachof the plurality of portions, said instruction executing unit performingthe operation specified by the first field using a portion specified bythe third field in a register specified by the second field.
 21. Theimage processing device as set forth in claim 20, wherein said variablelength code decoder outputs the second kind of image data to a memory,and said processor receives the second kind of image data from thememory.
 22. An image processing device comprising: a processor whichincludes an instruction decoder for decoding instructions of an imageprocessing program and an instruction executing unit for executing theinstructions responsive to outputs from said instruction decoder; and adata loader, which outputs image data for fixed length codes, whereinsaid processor is configured to perform a process of decoding a firstkind of image data variable length codes to a second kind of image dataof fixed length codes, a process of transforming the second kind ofimage data to a third kind of image data, and a process of prescribedoperation between the third kind of image data and the image data offixed length codes output from said data loader, and wherein theprocessor further includes a plurality of registers storing image data,each register having a plurality of portions, said instruction executingunit executes a prescribed instruction decoded by said instructiondecoder, the prescribed instruction having a first field specifyingcontents of an operation, a second field specifying a register number ofeach of said plurality of registers and a third field specifying each ofthe plurality of portions, said instruction executing unit performingthe operation specified by the first field using a portion specified bythe third field in a register specified by the second field.
 23. Theimage processing device as set forth in claim 22, wherein said dataloader outputs the image data of fixed length codes to a memory, andsaid processor receives the image data of fixed length codes from thememory.